User manual TEKTRONIX TLA7000 DATASHEET

[. . . ] In addition, the P6980 and P6982 can support the small voltage swings that differential signaling often requires. The P6962DBL, when used with a TLA7000 Series logic analyzer with the TLA7Bxx module, supports digital validation and debug of DDR3 memory with data rates up to 1600 mega-transfers per second. For board designs that do not include high-density probe footprints, the P6960 with its companion flying leadset provides the flexibility required to meet many different debug needs. P6800 and P6900 Series Probes No test and measurement solution is complete without probing. With the industry's lowest capacitance, the P6800 and P6900 Series logic analyzer probes protect the integrity of your signal ­ critical for connecting to fast buses like DDR2 and DDR3 where low intrusion is key to the proper operation of your design. [. . . ] 51 bits at 125 ps resolution (3. 25 days duration) Asynchronous/Synchronous 8 GHz MagniVu high-speed timing is available simultaneous with all modes 1 TLA7016 TL708EX Module "Merging" Environmental Characteristic Description Temperature Humidity Operating: +5 °C to +45 °C Nonoperating: ­20 °C to +60 °C 20% to 80% Operating: 30 °C; 80% relative humidity (29 °C maximum wet-bulb temperature) Nonoperating: 8% to 80% (29 °C maximum wet-bulb temperature) Operating: ­1, 000 ft. (­305 meters to 3, 050 meters) UL3111-1, CSA1010. 1, EN61010-1, IEC61010-1 Time Stamp Clocking/Acquisition Modes Number of Mainframe Instrument Slots Required per TLA Series Module Altitude Safety Physical Characteristics TLA7012 Portable Dimensions mm in. Input Characteristics (with P6800 or P6900 Series probes) Characteristic Description Capacitive Loading Height Width Depth Weight 295 451 460 kg 11. 6 17. 75 18. 1 lb. 0. 5 pF clock/data (P6900 Series) <0. 7 pF clock/data (P6800 Series) (1. 0 pF for P6810 in group configuration) From ­2. 0 V to +4. 5 V in 5 mV increments Threshold presets include TTL (1. 5 V), CMOS (1. 65 V), ECL (­1. 3 V), PECL (3. 7 V), LVPECL (2. 0 V), LVCMOS 1. 5 V (0. 75 V), LVCMOS 1. 8 V (0. 9 V), LVCMOS 2. 5 V (1. 25 V), LVCMOS 3. 3 V (1. 65 V), LVDS (0 V), and user defined Separate selection for each of the clock/qualifier channels and one per group of 16 data channels for each 34-channel probe ±(35 mV + 1%) Threshold Selection Range Net (w/o modules) Shipping (Typical) TLA7016 Benchtop Dimensions 14 27 mm 30 59 in. Threshold Selection Channel Granularity Threshold Accuracy (including probe) Input Voltage Range Operating Nondestructive Minimum Input Signal Swing Input Signal Minimum Slew Rate Height Width Depth Weight 350 425 673 kg 13. 7 16. 7 26. 5 lb. Net (w/o modules) Shipping (Typical) Dimensions 25 51. 8 mm 55 115 in. ­2. 5 V to 5. 0 V ±15 V 300 mV (single ended) ¯ VMAX ­ VMIN > 150 mV (differential) 200 mV/ns typical TL708EX 8-port Instrument Hub and Expander Height Width Depth Weight 51 445 305 kg 2 17. 5 12 lb. Net Shipping 3 5 6 11 www. tektronix. com 5 Data Sheet Timing Acquisition Characteristics (with P6800 or P6900 Series probes) Characteristic Description MagniVuTM Timing MagniVu Timing Record Length Deep Timing Resolution (Quarter/Half/Full channels) Deep Timing Resolution with Glitch Storage Enabled Deep Timing Record Length (Quarter/Half/Full channels with time stamps and with or without transitional storage) Deep Timing Record Length with Glitch Storage Enabled Channel-to-Channel Skew Minimum Recognizable Pulse/Glitch Width (Single channel) Minimum Detectable Setup/Hold Violation Minimum Recognizable Multichannel Trigger Event 125 ps max, adjustments to 250 ps, 500 ps, 1 ns, and 2 ns 16 Kb per channel, with adjustable trigger position 500 ps / 1 ns / 2 ns to 50 ms 4 ns to 50 ms 8/4/2 Mb, 32/16/8 Mb, 128/64/32 Mb, 512/256/128 Mb per channel State Acquisition Characteristics (with P6800 or P6900 Series probes) Full Channel Half Channel Quarter Channel 235 MHz 450 MHz Optional 450 MHz / 450 Mb/s or 470 Mb/s (DDR) 800 MHz / 800 Mb/s or 900 Mb/s (DDR) Description 450 MHz / 900 Mb/s 625 MHz / 1. 25 Gb/s Half of default main memory depth 300 ps typical 500 ps (P6960, P6964, P6980, P6982, P6860, P6864, P6880), 750 ps (P6810) 250 ps Sample period + channel-to-channel skew Characteristic State Record Length with Time Stamps Setup-and-Hold Time Selection Range (Quarter/Half/Full channels) 8/4/2 Mb, 32/16/8 Mb, 128/64/32 Mb, 512/256/128 Mb per channel From 16 ns before, to 8 ns after clock edge in 125 ps increments. Range may be shifted towards the setup region by 0 ns [+8, ­8] ns, 4 ns [+12, ­4] ns, or 8 ns [+16, 0] ns 625 ps typical 500 ps typical 500 ps (P6960, P6964, P6980, P6982, P6860, P6864, P6880), 700 ps (P6810) 400 ps Channels can be demultiplexed to other channels through user interface with 8-channel granularity Up to four "Fast Latches" per module (20 max per 5-way merge) to strobe source-synchronous buses into TLA7ACx modules. Four sets of any predefined "Fast Latches" may be combined with qualification data and data pipelining to store four independent source-synchronous data buses. Two "Fast Latches" may be combined to address DDR applications. Setup-and-Hold Window All channels Single channel Minimum Clock Pulse Width Active Clock Edge Separation Demux Channel Selection Source Synchronous Clocking Analog Acquisition Characteristics (with P6800 or P6900 Series probes) Characteristic Description Bandwidth Attenuation Offset and Gain (Accuracy) Channels Demultiplexed Run/Stop Requirements iCaptureTM Analog Outputs iCapture Analog Output BNC Cable 2 GHz typical 10X, ±1% ±50 mV, ±2% of signal amplitude 4 None, analog outputs are always active Compatible with any supported Tektronix oscilloscope Low loss, 10X, 36 in. Basic Analog Multiplexer functionality is offered standard on all TLA7ACx modules. Option AM enables full analog multiplexer control and allows the routing of any 4 logic analyzer channels to the iCapture Analog Output BNCs 6 www. tektronix. com Tektronix Logic Analyzers -- TLA7000 Series Trigger Characteristics Characteristic Description Physical Characteristics Dimensions mm in. Independent Trigger States Maximum Independent If/Then Clauses per State Maximum Number of Events per If/Then Clause Maximum Number of Actions per If/Then Clause Maximum Number of Trigger Events Number of Word Recognizers Number of Transition Recognizers Number of Range Recognizers Number of Counters/Timers Trigger Event Types 16 16 Height Width Depth Weight 262 61 381 kg 10. 3 2. 4 15 lb. 8 Net Shipping 3. 1 6. 3 6. 7 13. 7 8 TLA7Bxx Characteristics General Characteristic Description 18 (2 counters/timers plus any 16 other resources) 16 16 4 2 Word, Group, Channel, Transition, Range, Anything, Counter Value, Timer Value, Signal, Glitch, Setup-and-Hold Violation, Snapshot Trigger Module, Trigger All Modules, Trigger Main, Trigger MagniVu, Store, Don't Store, Store Sample, Increment Counter, Decrement Counter, Reset Counter, Start Timer, Stop Timer, Reset Timer, Snapshot Current Sample, Goto State, Set/Clear Signal, Do Nothing 1250 Mb/s (4X clocking mode) DC to 500 MHz (2 ns) 51 bits each (>50 days at 2 ns) DC to 500 MHz (2 ns) 500 MHz (2 ns) 2 ns Double bounded (408 channel max). Can be as wide as any group, must be grouped according to specified order of significance From 8 ns before to 7 ns after clock edge in 125 ps increments. This range may be shifted towards the positive region by 0 ns, 4 ns, or 8 ns From 7 ns before to 8 ns after clock edge in 125 ps increments. This range may be shifted towards the positive region by 0 ns [+8, ­8] ns, 4 ns [+12, ­4] ns, or 8 ns [+16, 0] ns Any data sample MagniVu position can be set from 0% to 60% centered around the MagniVu trigger Global (conditional), by state (start/stop), block, by trigger action, or transitional. Also force main prefill selection available Trigger Action Types Maximum Triggerable Data Rate Trigger Sequence Rate Counter/Timer Range Counter Rate Timer Clock Rate Counter/Timer Latency Range Recognizers Number of Channels (All channels are acquired including clocks) TLA7BB2 68 channels (4 are clock channels) TLA7BB3 102 channels (4 are clock, 2 are qualifier channels) TLA7BB4 136 channels (4 are clock, 4 are qualifier channels) TLA7BC4 136 channels (4 are clock, 4 are qualifier channels) (128 Mb) Channel grouping No limit to number of groups or number of channels per group (all channels can be reused in multiple groups) Module "Merging" Up to five 68-channel, 102-channel, or 136-channel modules can be "merged" to make up to a 680-channel module. Merged modules exhibit the same depth as the lesser of the five individual modules. Word/setup-and-hold/glitch/transition recognizers span all five modules. Time Stamp 54 bits at 20 ps resolution (>4 days duration) Clocking/Acquisition Modes Asynchronous and Synchronous. 20 ps (50 GHz) MagniVu, high-speed timing is available simultaneous with all modes 1 Number of Mainframe Instrument Slots Required per TLA Series Module Input Characteristics (with P6800 or P6900 Series probes) Characteristic Description Capacitive Loading Setup-and-Hold Violation Recognizer Setup Time Range Setup-and-Hold Violation Recognizer Hold Time Range Trigger Position MagniVu Trigger Position Storage Control (Data qualification) 0. 5 pF clock/data (P6900 Series) <0. 7 pF clock/data (P6800 Series); 1. 0 pF for P6810 when 8-channel podlet grouper is used Threshold Selection Range From ­2. 0 V to +4. 5 V in 5 mV increments Threshold presets include TTL (1. 5 V), CMOS (2. 5 V), ECL (­1. 3 V), PECL (3. 7 V), LVPECL (2. 0 V), LVCMOS 1. 5 V (0. 75 V), LVCMOS 1. 8 V (0. 9 V), LVCMOS 2. 5 V (1. 25 V), LVCMOS 3. 3 V (1. 65 V), LVDS (0 V), and user defined Threshold Selection Separate selection for each of the clock/qualifier and Channel Granularity individual channels Threshold Accuracy ±(35 mV + 1%) (including probe) Input Voltage Range ­2. 5 V to 5. 0 V Operating Nondestructive ±15 V Minimum Input Signal 200 mV (single ended) Swing V MAX ­ V MIN > 100 mV (differential) Input Signal Minimum Slew 200 mV/ns typical Rate www. tektronix. com 7 Data Sheet State Acquisition Characteristics (with P6800 or P6900 Series probes) Configuration Full Channel Half Channel 750 MHz Standard 1. 4 GHz Optional 750 MHz / 750 Mb/s (1 sample/clock) 750 MHz / 1. 5 Gb/s (2 samples/clock) 1. 4 GHz / 1. 4 Gb/s (1 sample/clock) Description 750 MHz / 3 Gb/s (4 samples/clock) 1. 4 GHz / 2. 8 Gb/s (2 samples/clock) Characteristic State Record Length with Time Stamps (Half/Full channels) Setup-and-Hold Time Selection Range Setup-and-Hold Window, Single Channel Minimum Clock Pulse Width 200 ps (P6960, P6964, P6980, P6982, P6860, P6864, P6880), 250 ps (P6810) Demux Channel Selection Channels can be demultiplexed to other channels through user interface with 8-channel granularity 4/2 Mb, 8/4 Mb, 16/8 Mb, 32/16 Mb, 64/32 Mb, 128/64 Mb per channel, 256/128 Mb per channel (TLA7BC4) From 15 ns before, to 7. 5 ns after clock edge in 20 ps increments. Range may be shifted towards the setup region by 0 ns [+7. 5, ­7. 5] ns, 2. 5 ns [+10, ­5] ns, or 7. 5 ns [+15, 0] ns 180 ps typical AutoDeskew and Customer Deskew Fixture Tektronix recommends AutoDeskew, a standard feature available within the TLA Application, for deskewing probe channels and setting the sample point for synchronous applications. However, for tight time alignment in both synchronous and asynchronous applications (including MagniVu), Tektronix recommends the Customer Deskew Fixture. This is an optional accessory to the TLA7Bxx modules that is used to perform a "channel-to-channel deskew" of the probes connected to the TLA7Bxx module to ensure tight time alignment between all channels across all probes. Two different fixtures are available: Timing Acquisition Characteristics (with P6800 or P6900 Series probes) Characteristic Description Customer Deskew Fixture for P6800 Series Probes Customer Deskew Fixture for P6900 Series Probes For ordering details, please see the Ordering Information section. MagniVuTM Timing MagniVu Timing Record Length Deep Timing Resolution (Quarter/Half/Full channels) Deep Timing Resolution with Glitch Storage Enabled Deep Timing Record Length (Quarter/Half/Full channels) 20 ps max, adjustments to 40 ps, 80 ps, 160 ps, 320 ps, and 640 ps 128 Kb per channel, with adjustable trigger position 156. 25 ps / 312. 5 ps / 625 ps to 50 ms 1. 25 ns to 50 ms Analog Acquisition Characteristics (with P6800 or P6900 Series probes) Characteristic Description 8/4/2 Mb, 16/8/4 Mb, 32/16/8 Mb, 64/32/16 Mb, 128/64/32 Mb, 256/128/64 Mb per channel; 512/256/128 (TLA7BC4) Deep Timing Record Length Half of default main memory depth with Glitch Storage Enabled Channel-to-Channel Skew (module + probes) Before customer deskew ±80 ps typical After customer deskew ±20 ps typical (see AutoDeskew information below) Minimum Recognizable 200 ps (P6960, P6964, P6980, P6982, P6860, Pulse/Glitch Width P6864, P6880) (Single channel) 250 ps (P6810) Minimum Detectable 40 ps Setup/Hold Violation Minimum Recognizable Sample period + channel-to-channel skew Multichannel Trigger Event Bandwidth Attenuation Offset and Gain (Accuracy) Channels Demultiplexed Run/Stop Requirements iViewTM Analog Outputs iView Analog Output BNC Cables 3 GHz (typical) 10X, ±1% ±50 mV, ±2% of signal amplitude 4 None, analog outputs are always active Compatible with any supported external Tektronix oscilloscope Four (4) low loss, 10X, 36 in. Physical Characteristics Dimensions mm in. Height Width Depth Weight 262 61 381 kg 10. 3 2. 4 15 lb. Net Shipping 3. 1 6. 3 6. 7 13. 7 8 www. tektronix. com Tektronix Logic Analyzers -- TLA7000 Series Trigger Characteristics Characteristic Description TLA7SAxx Characteristics General Characteristic Description Independent Trigger States Maximum Independent If/Then Clauses per State Maximum Number of Events per If/Then Clause Maximum Number of Actions per If/Then Clause Maximum Number of Trigger Events Number of Word Recognizers Number of Transition Recognizers Number of Range Recognizers Number of Counters/Timers Trigger Event Types 16 16 8 8 26 (2 counters/timers plus any 24 other resources) 24 24 8 Number of Lanes TLA7SA08 TLA7SA16 Record Length 2 Word, Group, Channel, Transition, Range, Anything, Counter Value, Timer Value, Signal, Glitch, Setup-and-Hold Violation, Snapshot Trigger Action Types Trigger Module, Trigger All Modules, Trigger Main, Trigger MagniVu, Store, Don't Store, Start Store, Stop Store, Increment Counter, Decrement Counter, Reset Counter, Start Timer, Stop Timer, Reset Timer, Snapshot Current Sample, Goto State, Set/Clear Signal, Do Nothing Maximum Triggerable Data 3. 0 Gb/s Rate Trigger Sequence Rate DC to 800 MHz (1. 25 ns) Counter/Timer Range 48 bits each (~4 days at 1. 25 ns) Counter Rate DC to 800 MHz (1. 25 ns) Timer Clock Rate 800 MHz (1. 25 ns) Counter/Timer Test Latency 0 ns Range Recognizers Double bounded (408 channel max). Can be as wide as any group, must be grouped according to specified order of significance Setup-and-Hold Violation Recognizer From 7. 5 ns before to 7. 5 ns after clock edge in 20 ps Setup time range increments. This range may be shifted towards the Hold time range positive region by 0 ns, 2. 5 ns, 5 ns, or 7. 5 ns Trigger Position Any data sample MagniVu Trigger Position MagniVu position can be set from 0% to 60% centered around the MagniVu trigger Storage Control All, Global (conditional), by state (start/stop), block, (Data qualification) by trigger action, or transitional. Also force main prefill selection available 8 lanes 16 lanes 8 GB x8 / 16 GB x16 with 160 MS per lane (160 ms at 8 Gb; 320 ms at 5 Gb; 640 ms at 2. 5 Gb at 100% bus utilization) 62 hours Time Stamp Range 54 bits at 25 ps resolution Time Stamp Clocking/Acquisition Modes TLA module without SSC (Spread Spectrum Clocking) , External Reference Clock (100 Mhz ±10% or 125 Mhz) with or without SSC External reference clock ±300 ppm frequency tolerance 1 Number of Mainframe Instrument Slots Required per TLA Series Module Module Configuration Requirements Module X1 Bi-Directional Link Width X4 X8 X16 TLA7SA08 TLA7SA16 1 1 1 1 0 1 0 2 Input Characteristics (with P6700 Series probes) Characteristic Description Capacitive Loading Minimum Data Eye See P6700 Series Probe Manual See P6700 Series Probe Manual Acquisition Characteristics (with P6700 Series probes) Characteristic Description Dynamic Link-width Switch Latency FTS Support Consumes up to 48 symbols (typical) PCIe Gen1&2: Consumes up to <12 FTS packets (typical) PCIe Gen3: Consumes <4 FTS packets (typical) Filter Characteristics Characteristic Description Ordered Sets DLLPs TLPs TS1, TS2, SKP, EIOS, FTS, EIEOS Ack, Nak, PM, Vendor Specific, InitFC1, InitiFC2, UpdateFC MRd, MRdL, MWr, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CPlLk, CPlDLk www. tektronix. com 9 Data Sheet Trigger Characteristics Characteristic Description Ordering Information Portable Logic Analyzer Mainframe, holds two TLA modules. [. . . ] G53 Complete Care 53 Years (includes loaner, scheduled calibration and more). R3DW Repair Service Coverage, 3 Years (includes product warranty period). R5DW Repair Service Coverage, 5 Years (includes product warranty period). 5-year period starts at time of instrument purchase X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X TLA7000 Series Upgrades You can add new capabilities to your existing TLA mainframe or increase the state speed, memory depth, or add full analog multiplexer capability (TLA7ACx only) to existing TLA modules by ordering the appropriate upgrade kit. [. . . ]