User manual INTEL CORE I7-900 DEKSTOP SPECIFICATION UPDATE

[. . . ] Intel® CoreTM i7-900 Desktop Processor Extreme Edition Series and Intel® CoreTM i7-900 Desktop Processor Series Specification Update April 2010 Notice: Intel® CoreTM i7-900 Desktop Processor Extreme Edition Series and Intel® CoreTM i7900 Desktop Processor Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. Document Number: 320836-015 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. [. . . ] Problem: For the steppings affected, see the Summary Table of Changes. C6 Transitions May Cause Spurious Updates to the xAPIC Error Status Register If any of the LVT entries are not initialized, reads from xAPIC Error Status Register following a C6 transition may report a spurious illegal vector received. Implication: Due to this erratum, reads to xAPIC Error Status Register may report illegal vector received when none was actually received. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Problem: For the steppings affected, see the Summary Table of Changes. Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write Major Mode Enabled Under a specific set of conditions, critical ISOCH (isochronous) traffic may cause unpredictable system behavior with write major mode enabled. Implication: Due to this erratum unpredictable system behavior may occur. Workaround: Write major mode must be disabled in the BIOS by writing the write major mode threshold value to its maximum value of 1FH in ISOCHEXITTRESHOLD bits [19:15], ISOCHENTRYTHRESHOLD bits [14:10], WMENTRYTHRESHOLD bits [9:5], and WMEXITTHRESHOLD bits [4:0] of the MC_CHANNEL_{0, 1, 2}_WAQ_PARAMS register. Problem: For the steppings affected, see the Summary Table of Changes. Running with Write Major Mode Disabled May Lead to a System Hang With write major mode disabled, reads will be favored over writes and under certain circumstances this can lead to a system hang. Intel® CoreTM i7 processor Specification Update 39 Errata Implication: Due to this erratum a system hang may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum Status: AAJ64. Problem: For the steppings affected, see the Summary Table of Changes. Memory Controller Address Parity Error Injection Does Not Work Correctly When MC_CHANNEL_{0, 1, 2}_ECC_ERROR_INJECT. INJECT_ADDR_PARITY bit [4] = 1 an error may be injected on any command on the channel and not just RD or WR CAS commands that match MC_CHANNEL_{0, 1, 2}_ADDR_MATCH. Implication: Address parity error injection cannot be used to reliably target a DIMM or memory location within a channel. When the address parity errors occur, the IA32_MCi_MISC register reflects the DIMM ID of the DIMM that detected error and not necessarily the DIMM that was targeted by the error injection settings. Problem: For the steppings affected, see the Summary Table of Changes. Memory Controller Opportunistic Refreshes Might be Missed If a system meets all 3 conditions below, opportunistic refresh capability might be degraded. 1. 2x refresh enabled and opportunistic refreshes enabled through tTHROT_OPPREFRESH field in the MC_CHANNEL_{0, 1, 2}_REFRESH_TIMING 2. DDR3-800 DIMMS or DDR3-1066 DIMMS with tREFI value programmed more than 5% lower than the nominal value 3. More than 2 DIMMs populated Implication: Due to this erratum, a corner condition can cause a persistent degradation of opportunistic refresh capability. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Problem: For the steppings affected, see the Summary Table of Changes. [. . . ] Due to this erratum the IA32_MC8_CTL2 MSR is not zeroed on processor warm reset. When this erratum occurs, the IA32_MC8_CTL2 MSR will not be zeroed by warm reset. Software that expects the values to be 0 coming out of warm reset may not behave as expected. Implication: Workaround: None identified. The Combination of a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to Processor Livelock Under certain complex micro-architectural conditions, the simultaneous occurrence of a page-split lock and several data accesses that are split across cacheline boundaries may lead to processor livelock. [. . . ]