User manual INTEL CORE I5-520E DATASHEET ADDENDUM

[. . . ] Intel® CoreTM i7-660UE, i7-620LE/ UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Datasheet Addendum August 2010 Document Number: 323178-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Legal Lines and Disclaimers Intel may make changes to specifications and product descriptions at any time, without notice. [. . . ] When a bit in this register is set, a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register. Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Datasheet Addendum August 2010 74 Document Number: 323178-003 Processor Configuration Registers Table 17. Error Command Registers Bit 15:12 11 Access RO RW Default Value 000b 0b RST/ PWR Core Core Reserved SERR on Processor Thermal Sensor Event (TSESERR): 1: The Processor generates a DMI SERR special cycle when bit 11 of the ERRSTS is set. The SERR must not be enabled at the same time as the SMI for the same thermal sensor event. Reserved SERR on LOCK to non-DRAM Memory (LCKERR): 1: The Processor will generate a DMI SERR special cycle whenever a CPU lock cycle is detected that does not hit DRAM. 0: Reporting of this condition via SERR messaging is disabled Reserved SERR on DRAM Throttle Condition (ERR): 0 = Reporting of this condition via SERR messaging is disabled. 1 = The memory controller generates a DMI SERR special cycle when a DRAM Read or Write Throttle condition occurs. Reserved SERR Multiple-Bit DRAM ECC Error (DMERR): 1: The Processor generates an SERR message over DMI when it detects a multiple-bit error reported by the DRAM controller. SERR on Single-bit ECC Error (DSERR): 1: The Processor generates an SERR special cycle over DMI when the DRAM controller detects a single bit error. Description 10 9 RO RW 0b 0b Core Core 8 7 RW RW 0b 0b Core Core 6:2 1 RO RW 00h 0b Core Core 0 RW 0b Core Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series August 2010 Datasheet Addendum Document Number: 323178-003 75 Processor Configuration Registers 6. 1. 4 SMICMD - SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI CC-CDh 0000h RO, RW; 16 bits This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. SMI Command Registers Bit 15:12 11 Access RO RW Default Value 0h 0b RST/ PWR Core Core Reserved SMI on Processor Thermal Sensor Trip (TSTSMI): 1: A SMI DMI special cycle is generated by Processor when the thermal sensor trip requires an SMI. A thermal sensor trip point cannot generate more than one special cycle. Reserved SMI on Multiple-Bit DRAM ECC Error (DMESMI): 1: The Processor generates an SMI DMI message when it detects a multiple-bit error reported by the DRAM controller. SMI on Single-bit ECC Error (DSESMI): 1: The Processor generates an SMI DMI special cycle when the DRAM controller detects a single bit error. Description 10:2 1 RO RW 000h 0b Core Core 0 RW 0b Core Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series Datasheet Addendum August 2010 76 Document Number: 323178-003 Processor Configuration Registers 6. 1. 5 C0WRDATACTRL - Channel 0 Write Data Control B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR 24D-24Fh 004111h RW 24 bits 00h Table 19. Channel 0 Write Data Control Registers Bit 23:16 Access RW Default Value 00h RST/ PWR Core Description ECC bit invert vector (C0sd_cr_eccbitinv): This vector operates individually for every ECC bit in the selected 64b ECC block, during write to DRAM. For all k between 0 and 7, when bit(k) is set to 1, the value for the k ECC bit (which corresponds with k data byte lane) is inverted. 15 RW 0b Core ECC Diagnostic Enable (C0sd_cr_eccdiagen): 1: The ECC bit invert vector is used to invert selected ECC bits, during writes to DRAM. 14:0 RW 4110h Core Reserved Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series August 2010 Datasheet Addendum Document Number: 323178-003 77 Processor Configuration Registers 6. 1. 6 COECCERRLOG - Channel 0 ECC Error Log B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/MCHBAR 280-287h 0000000000000000h RO-P; RO 64 bits This register is used to store the error status information in ECC enabled configurations, along with the error syndrome and the rank/bank/row/column address information of the address block of main memory of which an error (single bit or multibit error) has occurred. Note that the address fields represent the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software. Once the error flag bits are set as a result of an error, this bit field is locked and doesn't change as a result of a new error until the error flag is cleared by software. Same is the case with error syndrome field, but the following priority needs to be followed if more than one error occurs on one or more of the 4 QWs. MERR on QW0 MERR on QW1 MERR on QW2 MERR on QW3 CERR on QW0 CERR on QW1 CERR on QW2 CERR on QW3. [. . . ] Description 3 2:0 RO RO 0b 000b Core Core Reserved Extended VC Count (EVCC): Indicates the number of (extended) Virtual Channels in addition to the default VC supported by the device. 6. 3. 3 PVCCAP2 - Port VC Capability Register 2 B/D/F/Type: 0/6/0/MMR Address Offset: 108-10Bh Default Value:00000000h Access: RO; Size:32 bits Describes the configuration of PCI Express Virtual Channels associated with this port. Intel® CoreTM i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel® Celeron® Processor P4505, U3405 Series August 2010 Datasheet Addendum Document Number: 323178-003 135 Processor Configuration Registers Table 75. Bit 31:24 PVCCAP2 - Port VC Capability Register 2 Access RO Default Value 00h RST/PWR Core Description VC Arbitration Table Offset (VCATO): Indicates the location of the VC Arbitration Table. This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the Virtual Channel Capability Structure. A value of 0 indicates that the table is not present (due to fixed VC priority). 23:8 7:0 RO RO 0000h 00h Core Core Reserved Reserved for VC Arbitration Capability (VCAC) 6. 3. 4PVCCTL - Port VC Control B/D/F/Type:0/6/0/MMR Address Offset:10C-10Dh Default Value:0000h Access: RO; RW; Size:16 bits Table 76. Bit 15:4 3:1 PVCCTL - Port VC Control Access RO RW Default Value 000h 000b RST/PWR Core Core Reserved VC Arbitration Select (VCAS) This field is programmed by software to the only possible value as indicated in the VC Arbitration Capability field. Since there is no other VC supported than the default, this field is reserved. [. . . ]