User manual INTEL 6 SERIES CHIPSET DATASHEET 01-2011

[. . . ] Intel® 6 Series Chipset Datasheet January 2011 Document Number: 324645-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY O0R DEATH MAY OCCUR. [. . . ] When set to 1, the root port will not claim any downstream configuration transactions. 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 364 Datasheet Chipset Configuration Registers Bit 10:8 Description Root Port 3 Function Number (RP3FN) -- R/WO. This root port function number must be a unique value from the other root port function numbers Root Port 2 Config Hide (RP2CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. This root port function number must be a unique value from the other root port function numbers Root Port 1 Config Hide (RP1CH) -- R/W. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. This root port function number must be a unique value from the other root port function numbers 7 6:4 3 2:0 10. 1. 4 FLRSTAT--FLR Pending Status Register Offset Address: 0408­040Bh Default Value: 00000000h Bit 31:17 16 Reserved. Reserved. Attribute: Size: Description RO 32-bit 10. 1. 5 CIR2--Chipset Initialization Register 2 Offset Address: 0900­0901h Default Value: 0000h Bit 15:0 Attribute: Size: Description R/W 16-bit CIR2 Field 1 -- R/W. BIOS must program this field to 4000h. Datasheet 365 Chipset Configuration Registers 10. 1. 6 CIR3--Chipset Initialization Register 3 Offset Address: 1100­1101h Default Value: 0000h Bit 15:0 Attribute: Size: Description R/W 16-bit CIR3 Field 1 -- R/W. BIOS must program this field to 6000h. 10. 1. 7 TRSR--Trap Status Register Offset Address: 1E00­1E03h Default Value: 00000000h Bit 31:4 Reserved Cycle Trap SMI# Status (CTSS) -- R/WC. These bits are set by hardware when the corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped). These bits are OR'ed together to create a single status bit in the Power Management register space. 3:0 Note that the SMI# and trapping must be enabled in order to set these bits. These bits are set before the completion is generated for the trapped cycle, thereby ensuring that the processor can enter the SMI# handler when the instruction completes. Each status bit is cleared by writing a 1 to the corresponding bit location in this register. Attribute: Size: Description R/WC, RO 32-bit 10. 1. 8 TRCR--Trapped Cycle Register Offset Address: 1E10­1E17h Default Value: 0000000000000000h Attribute: Size: RO 64-bit This register saves information about the I/O Cycle that was trapped and generated the SMI# for software to read. Bit 63:25 24 23:20 19:16 Reserved Read/Write# (RWI) -- RO. This is the DWord-aligned byte enables associated with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in the cycle. Reserved Description 15:2 1:0 366 Datasheet Chipset Configuration Registers 10. 1. 9 TWDR--Trapped Write Data Register Offset Address: 1E18­1E1Fh Default Value: 0000000000000000h Attribute: Size: RO 64-bit This register saves the data from I/O write cycles that are trapped for software to read. Bit 63:32 31:0 Reserved Trapped I/O Data (TIOD) -- RO. Description 10. 1. 10 IOTRn--I/O Trap Register (0­3) Offset Address: 1E80­1E87h Register 0 1E88­1E8Fh Register 1 1E90­1E97h Register 2 1E98­1E9Fh Register 3 Default Value: 0000000000000000h Attribute: R/W Size: 64-bit These registers are used to specify the set of I/O cycles to be trapped and to enable this functionality. Bit 63:50 49 Reserved Read/Write Mask (RWM) -- R/W. 48 0 = Write 1 = Read NOTE: The value in this field does not matter if bit 49 is set. A 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. [. . . ] In loop back mode the value of this bit is written by hardware to the Modem Status Register bit 7. In loop back mode the value of this bit is written by hardware to Modem Status Register bit 6. In loopback mode, the value of this bit is written by hardware to Modem Status Register bit 4. In loopback mode, the value in this bit is written by hardware to Modem Status Register Bit 5. [. . . ]