User manual INTEL 500 DATASHEET REV 003

[. . . ] Intel® Celeron® Processor 500 Series Datasheet For Platforms Based on Mobile Intel® 965 Express Chipset Family January 2008 Revision 003 Document Number: 317665-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELÆ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. [. . . ] All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. Datasheet 53 Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 2 of 8) Name Type Description BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Celeron FSB agents. This includes debug or performance monitoring tools. Please refer to the platform design guide for more detailed information. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. The arbitration is done between processor (Symmetric Agent) and (G)MCH-M (High Priority Agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. The Intel® Celeron® processor 500 series for platforms based on the Mobile Intel® 965 Express Chipset family operates at a 533-MHz system bus frequency (133-MHz BCLK[1:0] frequency). COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the appropriate platform design guide for more details on implementation. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. D[63:0]# are quad-pumped signals and are driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups D[63:0]# Input/ Output Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DINV# 0 1 2 3 BPM[2:1]# BPM[3, 0]# Output Input/ Output BPRI# Input BR0# Input/ Output BSEL[2:0] Output COMP[3:0] Analog Furthermore, the DINV# pins determine the polarity of the data signals. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. 54 Datasheet Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 3 of 8) Name Type Description DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. [. . . ] The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The DTS relative temperature readout corresponds to an Intel Thermal Monitor 1 trigger point. When the DTS indicates maximum processor core temperature has been reached the Intel Thermal Monitor 1 hardware thermal control mechanism activates. The DTS and Intel Thermal Monitor 1 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die. [. . . ]