User manual INTEL 2ND GENERATION INTEL CORE PROCESSOR FAMILY DESKTOP DATASHEET VOLUME 1 01-2011

[. . . ] 2nd Generation Intel® CoreTM Processor Family Desktop Datasheet, Volume 1 Supporting Intel® CoreTM i7, i5 and i3 Desktop Processor Series This is Volume 1 of 2 January 2011 Document Number: 324641-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines and Disclaimers UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. [. . . ] Therefore, most applications are consuming less than the TDP at the rated frequency. To take advantage of the available thermal headroom, the active cores can increase their operating frequency. To determine the highest performance frequency amongst active cores, the processor takes the following into consideration: · The number of cores operating in the C0 state. Any of these factors can affect the maximum frequency for a given workload. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit. Note: Intel Turbo Boost Technology processor frequencies are only active if the operating system is requesting the P0 state. For more information on P-states and C-states, refer to Chapter 4, "Power Management". 3. 4. 2 Intel® Turbo Boost Technology Graphics Frequency Graphics render frequency is selected by the processor dynamically based on graphics workload demand. The processor can optimize both processor and Processor Graphics performance by managing power for the overall package. For the Processor Graphics, this allows an increase in the render core frequency and increased graphics performance for graphics intensive workloads. In addition, during processor intensive workloads when the graphics power is low, the processor core can increase its frequency higher within the package power limit. Enabling Intel Turbo Boost Technology will maximize the performance of the processor core and the graphics render frequency within the specified package power levels. Datasheet, Volume 1 39 Technologies 3. 5 Intel® Advanced Vector Extensions (AVX) Intel® Advanced Vector Extensions (AVX) is the latest expansion of the Intel instruction set. It extends the Intel® Streaming SIMD Extensions (SSE) from 128-bit vectors into 256-bit vectors. Intel AVX addresses the continued need for vector floating-point performance in mainstream scientific and engineering numerical applications, visual processing, recognition, data-mining/synthesis, gaming, physics, cryptography and other areas of applications. The enhancement in Intel AVX allows for improved performance due to wider vectors, new extensible syntax, and rich functionality including the ability to better manage, rearrange, and sort data. For more information on Intel AVX, see http://www. intel. com/software/avx 3. 6 Advanced Encryption Standard New Instructions (AES-NI) The processor supports Advanced Encryption Standard New Instructions (AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard (AES). AES-NI are valuable for a wide range of cryptographic applications; such as, applications that perform bulk encryption/decryption, authentication, random number generation, and authenticated encryption. AES is broadly accepted as the standard for both government and industry applications, and is widely deployed in various protocols. Four instructions, AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key expansion procedure. Together, these instructions provide a full hardware for supporting AES, offering security, high performance, and a great deal of flexibility. 3. 6. 1 PCLMULQDQ Instruction The processor supports the carry-less multiplication instruction, PCLMULQDQ. PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the 128-bit carry-less multiplication of two, 64-bit operands without generating and propagating carries. Carry-less multiplication is an essential processing component of several cryptographic systems and standards. Hence, accelerating carry-less multiplication can significantly contribute to achieving high speed secure computing and communication. 40 Datasheet, Volume 1 Technologies 3. 7 Intel® 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides a key mechanism for interrupt delivery. [. . . ] Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. More detailed information is provided in the Platform Environment Control Interface (PECI) Specification. 7. 11. 1 PECI Bus Architecture The PECI architecture based on wired OR bus that the clients (as processor PECI) can pull up high (with strong drive). Figure 7-1 demonstrates PECI design and connectivity, while the host/originator can be 3rd party PECI host, and one of the PECI clients is the processor PECI device. Figure 7-1. Example for PECI Host-clients Connection 84 Datasheet, Volume 1 Electrical Specifications 7. 11. 2 DC Characteristics The PECI interface operates at a nominal voltage set by VCCIO. [. . . ]